8255 Programmable Peripheral Interface (PPI)
Intel 8255A is a general purpose parallel I/O interface. The peripheral devices are slower than
the microprocessor. PPI makes an inter-relation between microprocessor and peripheral devices.
It provides three I/O port (Port A, Port B and Port C) and can be programmed as
a) Simple Parallel I/O (No handshaking)
b) Simple Strobe I/O (Use STB handshake)
c) Single Handshake I/O (Use STB-ACK handshake)
d) Double handshake I/O (Uses STB-ACK and STB-ACK)
Handshaking and Handshaking Signal
The making of inter relation between slower peripheral device and microprocessor is called
handshaking.
Before making the inter-relation between peripheral device and microprocessor the PPI send
some signals to microprocessor and peripheral device to perform the process, these signals are
called handshaking signal.
8255-based devices that perform handshaking support four handshaking signals:
• Strobe Input (STB)
• Input Buffer Full (IBF)
• Output Buffer Full (OBF)
• Acknowledge Input (ACK)
Use the STB and IBF signals for digital input operations and the OBF and ACK signals for
digital output operations. When the STB line is low, the samples are sent to the measurement
device. After the samples have been sent, IBF is high, which tells the peripheral device that the
data has been read. For digital output, OBF is low while the software sends the samples to a
peripheral device. After the peripheral device receives the samples, it sends a low pulse back on
the ACK line. Refer to your device documentation to determine which digital ports you can
configure for handshaking signals.
Parallel Data Transfer:
(a) Simple I/O: This data transfer method is used when the I/O devices need no
communication before the data transfer. Such devices are thermostat, LED. The crossed
lines on the wave form represent the time at which a new data byte becomes valid on the
output lines of the port.
(b) Simple Strobe I/O: The sending device, such as a keyboard, outputs parallel data on the
data lines, and then outputs an signal to let the receiving device know that valid data is
present.
(c) Single handshake Data transfer: The sending device outputs some parallel data and sends
an signal to the receiving device. The receiving device detects the asserted signal on a
polled or interrupt basis and reads in the byte of data. Then the receiving device send an
acknowledge signal to indicate that the data has been read. The sending device is
designed so that it doesn’t send the next data byte until the receiving device indicates
with an ACK signal.
(d) Double Handshake Data Transfer: The sending device asserts its line low to ask the
receiving device “are you ready?” The receiving device raises its ACK line high to say “I
am ready”. The peripheral device then sends the byte of data and raises its line high to
say “Here is some valid data for you”. After it has read in the data, the receiving data
drops its ACK line low to say “I have the data”. The receiving device is then ready to be
requested for accepting the next data byte.
The or ACK signals for these handshake transfers can be produced on a port pin by
instruction in the program. However, this method usually uses too much processor time. So,
parallel port device should be used. Example of such device is 8255A. The 8255A can be
programmed to function as follows-
• Receive an signal from a peripheral.
• Send an Interrupt signal to the processor.
• Send the ACK signal to the peripheral at proper time.
Difference between Latch and Buffer
Latch
A latch provides a means to "capture" the input data at a specific time via the use of a clock (for
edge triggered applications) or a strobe input (for level triggered applications)
A latch remembers the last state it was told to with another latching signal.
Buffer
A buffer is a device that provides additional current drive capability, typically used in bus
driving applications. Buffers are available in either inverting or non-inverting applications. They
are frequently available with 3-state outputs, so that their outputs can be removed from the bus
that they are driving. Buffers can be either unidirectional or bidirectional. Bidirectional buffers
have an additional input to determine which end is the input/output.
A buffer merely strengthens a signal so that it can be fanned out with integrity or drive a heftier
device. Any amplifier is a buffer. It outputs a state only as long as the state persists on its input(s).
8255A Internal Block Diagram
 |
| Fig: Block Diagram of the 8255 Programmable Peripheral Interface (PPI) |
the device. All information read from and written
to the 8255 occurs via these 8 data lines.
CS (Chip Select Input). If this line is a logical 0, the
microprocessor can read and write to the 8255.
RD (Read Input) Whenever this input line is a
logical 0 and the RD input is a logical 0, the 8255
data outputs are enabled onto the system data bus.
WR (Write Input) Whenever this input line is a
logical 0 and the CS input is a logical 0, data is
written to the 8255 from the system data bus
A0 - A1 (Address Inputs) The logical combination
of these two input lines determines which internal
register of the 8255 data is written to or read from.
RESET The 8255 is placed into its reset state if
this input line is a logical 1. All peripheral ports are
set to the input mode.
PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal
lines are used as 8-bit I/O ports. They can be
connected to peripheral devices. The 8255 has three
8 bit I/O ports and each one can be connected to the
physical lines of an external device. These lines are
labeled PA0-PA7, PB0-PB7, and PC0-PC7. The
groups of the signals are divided into three different
I/O ports labeled port A (PA), port B (PB), and port
C (PC).
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus.
Data is transmitted or received by the buffer upon execution of input or output instructions by the
CPU. Control words and status information are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and
Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn,
issues commands to both of the Control Groups.
(CS) Chip Select. A "low" on this input pin enables the communication between the 8255 and
the CPU.
(RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the
CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR)Write. A "low" on this input pin enables the CPU to write data or control words into the
8255.
(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and
WR inputs, control the selection of one of the three ports or the control word register. They are
normally connected to the least significant bits of the address bus (A0 and A1).
(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B,
C) are set to the input mode.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the
CPU "outputs" a control word to the 8255. The control word contains information such as
"mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each
of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control
logic, receives "control words" from the internal data bus and issues the proper commands to its
associated ports.
Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of
functional characteristics by the system software but each has its own special features or
"personality" to further enhances the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and
"pull-down" bus-hold devices are present on Port A.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).
This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a
4-bit latch and it can be used for the control signal output and status signal inputs in conjunction
with ports A and B.
Modes of Operation
To understand the modes of operation first we should know about control Word. A Control Word
is an 8-bit data that stored in control register. Control Word are two types:
1. Mode definition Control word- to tell the device what modes we want the ports to operate
in.
2. Bit Set/ Reset Control word- when we want to set or reset the output on a pin of port C.
BSRMode (Bit Set-Reset ControlWord): If bit 7 of control word is a logic o then 8255 will
be configured as BSR (Bit Set Rest) mode.
 |
| Fig: Control Word (Bit Set-Reset Control Word) formats for BSR Mode |
Problems: (a) Write a control word to reset PC5. (Ans: 0AH)
(b) Write a Control Word to Set PC2.
I/OMode (Mode Definition Control Word): If bit 7 of the control word is a logical 1 then the
8255 will be configured as I/O mode. I/O mode consists of Mode0, Mode1 and Mode2.
Mode0
• Port A works as simple input or output without handshaking.
• Port B works as simple input or output without handshaking.
• Port C can be used together as an additional 8 bit port or they can be used individually as two 4-bit ports
• When used as outputs, the Port C lines can be individually set or reset by sending a
special control word to the control register address.
Mode 1
- Used for handshake input/output operation.
- If port B is initialized in mode 1 for either input or output, Pins PC0, PC1 and PC2 function as handshake lines.
- If port A is initialized in mode 1 as handshake input, then pins PC3, PC4 and PC5
- function as handshake signals. (PC6 and PC7 are available for using as input lines or output lines)
- If port A is initialized as handshake output port, then PC3, PC6 and PC7 function as handshake signals. (PC4 and PC5 are available for using as input or output lines)
Mode 2
• Only port A can be initialized in mode 2.
• In mode 2, port A can be used for “bi-directional handshake” data transfer i.e. data can be input or output on the same eight lines.
• Pins PC3, PC4, PC5, PC6, PC7 used as handshake lines for port A
• Port B is operating in either mode 0 or mode 1.
• If port B is in mode 0, then PC0, PC1 and PC2 used for I/O .
• If port B is in mode 1, then PC0, PC1 and PC2 used as handshake lines.
8255A modes discussed above are summarized in the following table:
Examples:
Q1. Write an 8086 assembly language procedure to read an ASCII character from a keyboard via
PORT A of an 8255 PPI when PORT C bit PC4 is strobed low. Assume a base address of 20H.
Solution:
PORTA EQU 20H
PORTC EQU 22H
CONTROL EQU 23H
READ PROC NEAR
MOV AL, 98H ; 1001 1000
OUT CONTROL, AL ; Initialize PORTS
READ1:
IN AL, PORTC ; Is Strobe PC4 Low?
TEST AL, 10H ; 0001 0000
JNZ READ1
IN AL, PORTA ; Read ASCII Character
RET
READ ENDP
Q2. Write an 8086 assembly language procedure to send an ASCII character, stored in register
AH, to a printer via PORT B of an 8255 PPI when PORT C bit PCO is strobed low and after an
active low acknowledge signal is detected on PORT C bit PC5 from the printer. Assume a base
address of 60H.
Solution:
PORTB EQU 61H
PORTC EQU 62H
CONTROL EQU 63H
PRINT PROC NEAR
MOV AL, 88H ; 1000 1000
OUT CONTROL, AL
PRINT1:
IN AL, PORTC ; Is Acknowledge PC5 Low?
TEST AL, 20H ; 0010 000
JNZ PRINT1
;-------------------------------------
MOV AL, AH ; send character
OUT PORTB, AL
;-------------------------------------
MOV AL, 0FEH ; 1111 1110
OUT PORTC, AL ; strobe output PC0
RET
PRINT ENDP
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